ECE 5560
Transcript Abbreviation:
Adv Hardware Arch
Course Description:
This course introduces highly-practical methodologies and techniques that can be broadly used to improve the efficiency and achieve speed-area-power tradeoffs in the design of application-specific hardware implementation architectures for various algorithms. Efficient implementation architectures of commonly used arithmetic and digital signal processing functional blocks will also be discussed.
Course Levels:
Undergraduate (1000-5000 level)
Graduate (5000-8000 level)
Designation:
Elective
General Education Course:
(N/A)
Cross-Listings:
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
(N/A)
Select if Repeatable:
Off
Maximum Repeatable Credits:
(N/A)
Total Completions Allowed:
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 2050, and prereq or concur: 3561 or 3050; or Grad standing in Engr; or permission of instructor.
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 5194.08.
Course Goals / Objectives:
Students are exposed to advanced definitions and concepts relevant to the design of digital logic architectures.
Students become familiar with hardware architecture design methodologies for trading off speed, silicon area, and power
consumption.
consumption.
Students become competent in the design of efficient architectures for commonly used arithmetic and digital signal processing
functional blocks.
functional blocks.
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC out-of-class | REC in-class | Weekly LAB out-of-class | Weekly LAB in-class |
|---|---|---|---|---|---|
| Characteristics and representations of signal processing programs | 1.0 | 0.0 | 0 | 0.0 | 0 |
| Iteration bound | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Pipelining and parallel processing | 3.5 | 0.0 | 0 | 0.0 | 0 |
| Retiming | 3.5 | 0.0 | 0 | 0.0 | 0 |
| Unfolding | 3.5 | 0.0 | 0 | 0.0 | 0 |
| Folding | 3.5 | 0.0 | 0 | 0.0 | 0 |
| Fast Convolution | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Algorithmic strength reduction in filters and transformations | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Pipelined and parallel recursive filters | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Bit-level arithmetic architecture | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Redundant Arithmetic | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Numerical strength reduction | 1.0 | 0.0 | 0 | 0.0 | 0 |
| Various implementation topics | 6.0 | 0.0 | 0 | 0.0 | 0 |
| Total | 39 | 0 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Midterm 1 | 30% |
| Midterm 2 | 30% |
| Final project | 40% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, 1999. ISBN 0-471-24186-5 | K. K. Parhi |
ABET-CAC Criterion 3 Outcomes:
(N/A)
ABET-ETAC Criterion 3 Outcomes:
(N/A)
ABET-EAC Criterion 3 Outcomes:
| Significant contribution (7+ hours) | 1 | an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics |
| Substantial contribution (3-6 hours) | 2 | an ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors |
| Significant contribution (7+ hours) | 7 | an ability to acquire and apply new knowledge as needed, using appropriate learning strategies |
Embedded Literacies Info: