ECE 7023
Transcript Abbreviation:
High-Speed I/O ICs
Course Description:
Analysis and design of link architectures and circuits for wireline communication systems. Emphasis on design intuition, link budgeting and power/performance trade-offs in implementation of data links in advanced CMOS process. Topics include channel characterization, noise analysis, equalization, transmitter and receiver circuits, signaling schemes, clocking, synchronization and timing recovery
Course Levels:
Graduate (5000-8000 level)
Designation:
Elective
General Education Course:
(N/A)
Cross-Listings:
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
3.00
Select if Repeatable:
Off
Maximum Repeatable Credits:
(N/A)
Total Completions Allowed:
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq or concur: 5020 and 5021, or permission of instructor.
Electronically Enforced:
No
Exclusions:
(N/A)
Course Goals / Objectives:
Learn fundamentals of high-speed data link design
Learn system architecture using modeling tools
Understand the challenges of designing high-speed wireline circuits through a design project using advanced CMOS process.
Be exposed to several link standards, including USB-Type C, Thunderbolt, PCIe and DDR.
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC out-of-class | REC in-class | Weekly LAB out-of-class | Weekly LAB in-class |
|---|---|---|---|---|---|
| Basic high-speed data link concepts | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Channel characterization | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Performance metrics, link budget and trade-offs | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Equalization | 6.0 | 0.0 | 0 | 0.0 | 0 |
| Signaling schemes | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Transmitter circuits | 5.0 | 0.0 | 0 | 0.0 | 0 |
| Receiver circuits | 6.0 | 0.0 | 0 | 0.0 | 0 |
| Clocking, synchronization and timing recovery | 5.0 | 0.0 | 0 | 0.0 | 0 |
| Power and clock distribution | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Project presentations | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Total | 39 | 0 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Quizzes | 20% |
| Exam I | 20% |
| Exam II | 20% |
| Design Projects | 40% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| No Text book needed. Lecture Handouts |
ABET-CAC Criterion 3 Outcomes:
(N/A)
ABET-ETAC Criterion 3 Outcomes:
(N/A)
ABET-EAC Criterion 3 Outcomes:
(N/A)
Embedded Literacies Info: