ECE 6244
Transcript Abbreviation:
Des & Proc WBG Dev
Course Description:
Design and processing of wide band gap power devices (including SiC, GaN and ultra wide band gap semiconductors) and reliability considerations. 2D device simulations, layout considerations for power chip from 600 V to 15 kV.
Course Levels:
Graduate (5000-8000 level)
Designation:
Elective
General Education Course:
(N/A)
Cross-Listings:
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
3.00
Select if Repeatable:
Off
Maximum Repeatable Credits:
(N/A)
Total Completions Allowed:
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Distance Learning (100% online)
Prerequisites and Co-requisites:
Prereq: Grad standing in Engineering or Physics.
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 6234.
Course Goals / Objectives:
Provide an introduction to basic operation of WBG power devices
Students master design principles and 2D simulations of power devices
Students become competent with layout of power device chips
Students are exposed to the processing details of power devices
Students become familiar with reliability and qualification of power devices
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC out-of-class | REC in-class | Weekly LAB out-of-class | Weekly LAB in-class |
|---|---|---|---|---|---|
| Review of semiconductor basics | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Operation and characteristics of the SiC Schottky Barrier Diode, SiC DMOSFET and GaN HEMT | 4.0 | 0.0 | 0 | 0.0 | 0 |
| 2D simulations of 1700 VSiC Schottky Barrier Diode, DMOSFETS and 600 V GaN HEMT and design considerations for edge termination, dv/dt, short circuit time, avalanche ruggedness, design for HTRB, optimization of on-resistance etc. | 9.0 | 0.0 | 0 | 0.0 | 0 |
| Process Integration: Overall process sequence for SiC Schottky Diode, SiC MOSFET and GaN HEMT and unit processes | 9.0 | 0.0 | 0 | 0.0 | 0 |
| Layout of the 1700 V SiC Schottky Barrier Diode, DMOSFET and 600 V GaN HEMT | 9.0 | 0.0 | 0 | 0.0 | 0 |
| Misc. Topics: Thermal and yield considerations, qualification and reliability, cost of manufacturing, availability of substrates and epilayers, worldwide manufacturing of SiC and GaN devices and supply chain | 5.0 | 0.0 | 0 | 0.0 | 0 |
| Total | 40 | 0 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homework | 50% |
| Final Take Home Project | 50% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| No Textbooks and Other Course Materials Entered. | ||
ABET-CAC Criterion 3 Outcomes:
(N/A)
ABET-ETAC Criterion 3 Outcomes:
(N/A)
ABET-EAC Criterion 3 Outcomes:
(N/A)
Embedded Literacies Info: