ECE 5031
Transcript Abbreviation:
Semicon Proc Tech
Course Description:
Discrete and integrated circuit device design, silicon VLSI processing technologies, III-V compound semiconductor device fabrication technologies; epitaxy, doping, bandgap engineering; and device measurements and failure mechanisms.
Course Levels:
Undergraduate (1000-5000 level)
Graduate (5000-8000 level)
Designation:
Elective
General Education Course:
(N/A)
Cross-Listings:
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
(N/A)
Select if Repeatable:
Off
Maximum Repeatable Credits:
(N/A)
Total Completions Allowed:
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 3030, or Grad standing in Engineering, Biological Sciences, or Math and Physical Sciences.
Electronically Enforced:
No
Exclusions:
(N/A)
Course Goals / Objectives:
Learn about the processing technologies used for fabrication of silicon VLSI integrated circuits
Develop an understanding of process integration for NMOS, CMOS and MOS memory IC technology
Exposed to silicon process information pertinent to the interface between process engineers and integrated circuit design engineers
Learn about processing technology of compound semiconductors
Learn about methods and techniques used for fabricating compound semiconductor devices used in communications, optoelectronics, high speed wireless applications
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC out-of-class | REC in-class | Weekly LAB out-of-class | Weekly LAB in-class |
|---|---|---|---|---|---|
| Overview of CMOS process | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Lithography – contact, projection, e-beam | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Vacuum and ultra-high vacuum physics and technology | 2.0 | 0.0 | 0 | 0.0 | 0 |
| CVD and silicon epitaxy | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Wet chemical processing | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Plasma processing (etching, sputtering, PECVD) | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Atomic layer deposition | 1.0 | 0.0 | 0 | 0.0 | 0 |
| Ion implantation and diffusion | 4.0 | 0.0 | 0 | 0.0 | 0 |
| Back end processing – interconnects and CMP | 2.0 | 0.0 | 0 | 0.0 | 0 |
| CMOS and MOS memory process integration | 4.0 | 0.0 | 0 | 0.0 | 0 |
| III-V semiconductor bulk crystal growth techniques | 1.0 | 0.0 | 0 | 0.0 | 0 |
| Semiconductor epitaxial growth methods - molecular beam epitaxy and metal organic CVD | 1.0 | 0.0 | 0 | 0.0 | 0 |
| Ohmic contact formation for III_V and III-nitride semiconductors | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Compound semiconductor device process integration | 3.0 | 0.0 | 0 | 0.0 | 0 |
| Schottkey contact formation for III-V and III-nitride semiconductors | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Fabrication of III-V and III-nitride semiconductor diodes and transistors | 2.0 | 0.0 | 0 | 0.0 | 0 |
| Total | 40 | 0 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homework | 15% |
| Midterm 1 | 25% |
| Midterm 2 | 25% |
| Final exam | 35% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Fabrication Engineering at the Micro- and Nanoscale | Stephen A. Campbell |
ABET-CAC Criterion 3 Outcomes:
(N/A)
ABET-ETAC Criterion 3 Outcomes:
(N/A)
ABET-EAC Criterion 3 Outcomes:
| Significant contribution (7+ hours) | 1 | an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics |
| Some contribution (1-2 hours) | 3 | an ability to communicate effectively with a range of audiences - pre-2019 EAC SLO (g) |
| Substantial contribution (3-6 hours) | 6 | an ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions |
| Some contribution (1-2 hours) | 7 | an ability to acquire and apply new knowledge as needed, using appropriate learning strategies |
Embedded Literacies Info: