CSE 6422
Transcript Abbreviation:
Advanced Comp Arch
Course Description:
Fundamental design issues in parallel architectures, design of scalable shared memory and distributed memory systems, interconnection networks (on-chip and off-chip), multi-core architectures, accelerators, embedded systems, and exascale systems.
Course Levels:
Graduate
Designation:
Elective
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
3.00
Select if Repeatable:
Off
Maximum Repeatable Credits
(N/A)
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 6421 (775) and 6441 (721).
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 875.
Course Goals / Objectives:
Master the principles of advanced computer architecture
Master the implications of different ways of using hardware parallelism (processors, interconnection networks and accelerators)
Master the architectural design issues in shared memory, distributed-memory, distributed shared memory, and petascale/exascale systems
Master the design principles of interconnection networks
Be familiar with the architectural designs of past and present (state-of-the-art) computer systems
Be familiar with analyzing and solving architectural design problems
Be exposed to the future trends in parallel computer architectures
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Design issues of Parallel Architectures | 3.0 | 0.0 | 0.0 | 0 |
| Interconnection Network Design Principles (Classification of interconnection networks, basic switching techniques, virtual channels) | 3.0 | 0.0 | 0.0 | 0 |
| Design Principles (Cont'd): Deadlock, Livelock, and Starvation; Routing Algorithms for direct, indirect, and switch-based networks; System support, hardware implementations, and software implementations for collective communication | 6.0 | 0.0 | 0.0 | 0 |
| Latest Multi-core Architectures | 3.0 | 0.0 | 0.0 | 0 |
| On-Chip Interconnect Architectures | 3.0 | 0.0 | 0.0 | 0 |
| Design of Shared-Memory Multiprocessors (Cache Coherence, Memory Consistency, Snooping Protocols, Protocol Design Tradeoffs, Synchronization, and Implications on Software) | 4.0 | 0.0 | 0.0 | 0 |
| Snoop-based Multiprocessor (Symmetric Multiprocessor) Design (Single-level cache with an atomic bus, multi-level cache hierarchies and split-transaction bus.) | 5.0 | 0.0 | 0.0 | 0 |
| Acclerator Architectures | 3.0 | 0.0 | 0.0 | 0 |
| Issues in Designing Scalable Systems (DSM Systems with Directory-based Cache Coherence, Software DSM Systems, and Scalable Non Cache Coherent Systems Supporting PGAS Models) | 3.0 | 0.0 | 0.0 | 0 |
| Architectural Issues in Designing Power-Aware and Embedded Computing Systems | 3.0 | 0.0 | 0.0 | 0 |
| Overview of Current Multi-Petaflop Systems and Architecture for Emerging Exascale Systems | 6.0 | 0.0 | 0.0 | 0 |
| Total | 42 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homeworks | 15% |
| Final Exam | 40% |
| Project | 35% |
| Class Participation and Discussion | 10% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Parallel Computer Architecture: A Hardware/Software Approach | David Culler, Jaswinder Pal Singh and Anoop Gupta | |
| Interconnection Networks: An Engineering Approach | Jose Duato, Sudhakar Yalamanchili and Lionel Ni |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes
(N/A)
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)