ECE 5362
Transcript Abbreviation:
Cmptr Arch/Design
Course Description:
Design of general purpose digital computers including arithmetic and control units, input/output, and memory subsystems.
Course Levels:
Undergraduate (1000-5000 level)
Graduate
Designation:
Required
Elective
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours
(N/A)
Select if Repeatable:
Off
Maximum Repeatable Credits
(N/A)
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 2560 and 3561, and undergraduate enrollment in ECE, CSE, or EngPhysics major; or Grad standing in Engineering.
Electronically Enforced:
No
Exclusions:
Not open to students with credit for CSE 3421.
Course Goals / Objectives:
Be competent with typical assembly/machine instructions, as well as the key architecture design principles such as RISC vs. CISC.
Master designing control unit systems to meet the requirements of the instruction set given the computer registers and hardware
Be competent with CPU control design tools
Master memory/cache system design algorithms such as cache mapping and replacement
Be familiar with advanced architectural features such as pipelining, fast adder, and fast multiplication.
Be exposed to embedded systems
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Design of computer registers, buses, and control lines with timing considerations | 5.0 | 0.0 | 0.0 | 0 |
| Instruction sets and their implementation in register transfers | 6.0 | 0.0 | 0.0 | 0 |
| Hardwired and microprogrammed control units | 4.0 | 0.0 | 0.0 | 0 |
| Simulation of control units using software to verify correctness of control unit design | 4.0 | 0.0 | 0.0 | 0 |
| Memory units including cache memory | 5.0 | 0.0 | 0.0 | 0 |
| Input/Output systems including polling, interrupt and DMA | 3.0 | 0.0 | 0.0 | 0 |
| Fast multiplication and floating point operations | 5.0 | 0.0 | 0.0 | 0 |
| Basic processing unit and pipelining | 5.0 | 0.0 | 0.0 | 0 |
| Embedded systems | 1.0 | 0.0 | 0.0 | 0 |
| Total | 38 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homework | 14% |
| Computer problems | 16% |
| Midterm Exams | 40% |
| Final Exam | 30% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Computer Organization and Embedded Systems | Hamacher, Vranesic, Zaky and Manjikian |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes:
| Outcome | Contribution | Description |
|---|---|---|
| 1 | Substantial contribution (3-6 hours) | an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics |
| 5 | Some contribution (1-2 hours) | an ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives |
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)