ECE 2061
Transcript Abbreviation:
IntDigitalLogicLec
Course Description:
Lecture-only component of ECE 2060, for transfer students. Introduction to the theory and practice of combinational and clocked sequential networks.
Course Levels:
Undergraduate (1000-5000 level)
Designation:
Elective
Required
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
2.50
Max Credit Hours:
2.50
Select if Repeatable:
Off
Maximum Repeatable Credits
(N/A)
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Hybrid Class (25-74% campus; 25-74% online)
Prerequisites and Co-requisites:
Prereq: Math 1152 or 1161.01 or 1161.02 or 1172 or 1181H, and Physics 1250, 1250H or 1260, and CSE 1222 or 2221 or Engr 1281.01H or 1281.02H or 1222; and Engr 1182.01 or 1182.02 or 1182.03 or 1282.01H or 1282.02H or 1282.03H, or Engr 1186 and 1187. and concur: 1188 concurrent, or 1187 and 1188 and concur: 1186, or major in CIS or CIS-PRE; and CPHR 2.00 or above.
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 2000, 2000.02, 2001, 2010, or 2060.
Course Goals / Objectives:
Master the number representations used in today's digital systems and their arithmetic properties and conversion techniques
Master analyzing and synthesizing networks of combinatorial, digital logic elements
Be competent to analyze, design and synthesize digital clocked sequential circuits
Be familiar with modern computer tools for digital design, verification and simulation
Be familiar with digital circuit design methods
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Number systems and conversion | 3.0 | 0.0 | 0.0 | 0 |
| Boolean algebra | 2.0 | 0.0 | 0.0 | 0 |
| Karnaugh maps | 2.0 | 0.0 | 0.0 | 0 |
| Multi-level gate circuits | 2.0 | 0.0 | 0.0 | 0 |
| Multiplexers, decoders and PLDs | 3.0 | 0.0 | 0.0 | 0 |
| Latches and flip-flops | 3.0 | 0.0 | 0.0 | 0 |
| Registers and counters | 3.0 | 0.0 | 0.0 | 0 |
| Timing (delays, timing diagrams) | 2.0 | 0.0 | 0.0 | 0 |
| Analysis of clocked sequential circuits (general models for sequential circuits, timing charts, state tables, graphs) | 4.0 | 0.0 | 0.0 | 0 |
| Design of clocked sequential circuits | 4.0 | 0.0 | 0.0 | 0 |
| Finite state machines, flow diagrams, mapping to flip-flop circuits with logic gates. | 4.0 | 0.0 | 0.0 | 0 |
| Total | 32 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homework | 20% |
| Midterm Exam 1 | 25% |
| Midterm Exam 2 | 25% |
| Final Exam | 30% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Fundamentals of Logic Design | Roth, Jr. and Kinney |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes
(N/A)
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)