CSE 6421
Transcript Abbreviation:
Comp Arch
Course Description:
Principles and tradeoffs behind the design of modern computer architectures, including instruction-level parallelism, memory system design, advanced cache architectures, cache coherence, multiprocessors, energy-efficient and embedded architectures.
Course Levels:
Graduate
Designation:
Elective
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
3.00
Select if Repeatable:
Off
Maximum Repeatable Credits
(N/A)
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 3431 (660) or 5431, and 3421 (675), 5421, or ECE 5362 (662).
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 775.
Course Goals / Objectives:
Master quantitative and qualitative design issues in modern architectures
Master techniques for exploiting instruction-level parallelism
Be familiar with instruction set architecture design principles
Be familiar with multiprocessors and thread-level parallelism
Be familiar with memory system design
Master advanced cache architectures and cache coherence
Be exposed to energy-efficient microprocessor design
Be exposed to vector and VLIW architectures
Be exposed to emerging directions in computer architecture
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Quantitative and qualitative design principles and introduction to modern computer architectures | 5.0 | 0.0 | 0.0 | 0 |
| Instruction set design principles | 2.0 | 0.0 | 0.0 | 0 |
| Techniques for exploiting instruction-level parallelism | 11.0 | 0.0 | 0.0 | 0 |
| Multiprocessors and thread-level parallelism | 6.0 | 0.0 | 0.0 | 0 |
| Memory system design, advanced cache architectures, cache coherence | 8.5 | 0.0 | 0.0 | 0 |
| Energy-efficient microprocessor design | 3.0 | 0.0 | 0.0 | 0 |
| Vector and VLIW architectures | 3.0 | 0.0 | 0.0 | 0 |
| Architectures for embedded systems | 2.0 | 0.0 | 0.0 | 0 |
| Emerging directions in computer architecture | 1.5 | 0.0 | 0.0 | 0 |
| Total | 42 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homework assignments | 20% |
| Laboratory assignments | 20% |
| Midterm | 25% |
| Final exam | 35% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Computer Architecture: A Quantitative Approach | John Hennessy and David Patterson, Morgan Kauffman, 2007 |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes
(N/A)
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)