ECE 5020
Transcript Abbreviation:
Mixed Signal VLSI
Course Description:
Design and circuit analysis of basic VLSI structures such as registers, cell libraries, digital and analog I/O. Physical layout, timing analysis, PLLs, design tools.
Course Levels:
Undergraduate (1000-5000 level)
Graduate
Designation:
Elective
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours
(N/A)
Select if Repeatable:
Off
Maximum Repeatable Credits
(N/A)
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Distance Learning (100% online)
Prerequisites and Co-requisites:
Prereq: 3020, or Grad standing in Engineering, Biological Sciences, or Math and Physical Sciences.
Electronically Enforced:
No
Exclusions
(N/A)
Course Goals / Objectives:
Be familiar with integrated circuit design flows and project planning
Be competent in CMOS circuit performance characterization using CAD tools
Master the analysis and design of CMOS logic circuits
Be competent in clean physical layout of standard CMOS logic cells using CAD tools
Be competent in analysis and design of arithmetic logic building blocks and memo
Be exposed to system design, including interconnect, clocking and power distribution.
Be competent in working effectively in a team to complete a design project.
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Design flow and project planning | 4.0 | 0.0 | 0.0 | 0 |
| CMOS circuit and logic design | 6.0 | 0.0 | 0.0 | 0 |
| MOS transistor equations and circuit performance characterization - speed, power, reliability. | 8.0 | 0.0 | 0.0 | 0 |
| CMOS fabrication, design rules, and physical layout | 6.0 | 0.0 | 0.0 | 0 |
| Use of CAD tools, circuit simulation techniques | 5.0 | 0.0 | 0.0 | 0 |
| System design, array subsystems, special purpose systems - clocking, I/O pads, analog | 10.0 | 0.0 | 0.0 | 0 |
| Total | 39 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Homework and Quizzes | 15% |
| Exam I | 30% |
| Design Report | 20% |
| Final Exam | 35% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Digital Integrated Circuits | Rabeay, Chandrakasan, Nikolic |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes:
| Outcome | Contribution | Description |
|---|---|---|
| 1 | Significant contribution (7+ hours) | an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics |
| 2 | Significant contribution (7+ hours) | an ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors |
| 6 | Some contribution (1-2 hours) | an ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions |
| 7 | Significant contribution (7+ hours) | an ability to acquire and apply new knowledge as needed, using appropriate learning strategies |
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)