ECE 3561
Transcript Abbreviation:
Adv Digital Dsgn
Course Description:
Design and analysis of sequential circuits; digital circuit design using building blocks, programmable logic devices; design of basic computer components such as arithmetic logic units.
Course Levels:
Undergraduate (1000-5000 level)
Designation:
Required
Elective
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours
(N/A)
Select if Repeatable:
Off
Maximum Repeatable Credits
(N/A)
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 2000, 2060, 2061, 2010, 2000.02, 290, 294 (Autumn 2010) or 206 and 261. Prereq or concur: 3020 (323), and enrollment in ECE, EngPhys, or CSE majors; or prereq or concur 2010 and permission of department.
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 561.
Course Goals / Objectives:
Learn digital design principles and practice and learn to design using building blocks such as counters, shift registers, and adders and programmable logic devices such as FPGAs and CPLD
Learn methods to design clocked sequential circuits using state diagrams and tables, state reduction and state assignment methods
Learn to perform timing analysis at each step of the design
VHDL is introduced
Design and simulate digital circuits using a state-of-the-art CAD package. Both schematic and VHDL-based design is supported
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Clocked synchronous state-machine analysis and timing | 8.0 | 0.0 | 0.0 | 0 |
| Clocked synchronous state-machine design | 13.0 | 0.0 | 0.0 | 0 |
| Design with counters, shift registers, multiplexers, comparators, decoders, and adders | 8.0 | 0.0 | 0.0 | 0 |
| Design with asynchronous inputs and for glitch-free outputs | 1.0 | 0.0 | 0.0 | 0 |
| VHDL for combinational logic and state machine design | 4.0 | 0.0 | 0.0 | 0 |
| Logic implementation with PLDs, FPGAs, and ROMs | 6.0 | 0.0 | 0.0 | 0 |
| Total | 40 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Quizzes | 15% |
| Computer Projects & Homework | 30% |
| Midterm Exams | 25% |
| Final Exam | 30% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| Fundamentals of Logic Design Roth and Kinney | Roth and Kinney |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes:
| Outcome | Contribution | Description |
|---|---|---|
| 1 | Substantial contribution (3-6 hours) | an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics |
| 2 | Substantial contribution (3-6 hours) | an ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors |
| 4 | Some contribution (1-2 hours) | an ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts |
| 5 | Substantial contribution (3-6 hours) | an ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives |
| 6 | Substantial contribution (3-6 hours) | an ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions |
| 7 | Substantial contribution (3-6 hours) | an ability to acquire and apply new knowledge as needed, using appropriate learning strategies |
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)