ECE 5462
Transcript Abbreviation:
HDL Dsgn and Verif
Course Description:
The detailed design and verification of major components of a computer architecture using a standard hardware description language (HDL).
Course Levels:
Undergraduate (1000-5000 level)
Graduate
Designation:
Elective
General Education Course
(N/A)
Cross-Listings
(N/A)
Credit Hours (Minimum if “Range”selected):
3.00
Max Credit Hours:
3.00
Select if Repeatable:
Off
Maximum Repeatable Credits:
3.00
Total Completions Allowed
(N/A)
Allow Multiple Enrollments in Term:
No
Course Length:
14 weeks (autumn or spring)
12 weeks (summer only)
Off Campus:
Never
Campus Location:
Columbus
Instruction Modes:
In Person (75-100% campus; 0-24% online)
Prerequisites and Co-requisites:
Prereq: 5362, or 561 and 662, or CSE 675.01 or equiv, or Grad standing in Engineering.
Electronically Enforced:
No
Exclusions:
Not open to students with credit for 762 or 764.
Course Goals / Objectives:
Introduce design of major components of computer architecture
Introduce basic concepts of hardware description languages (HDL)
Learn to use VHDL to specify, design, and model digital hardware components
Learn functional verification and implement a verification plan on HDL designs. Verification of a complex component and a system of several components is done
Learn to use HDL computer aided design tools
Check if concurrence sought:
No
Contact Hours:
| Topic | LEC | REC | LAB | LAB Inst |
|---|---|---|---|---|
| Advanced logic design techniques, computer architecture | 6.0 | 0.0 | 0.0 | 0 |
| Basic of a Hardware Description Language | 6.0 | 0.0 | 0.0 | 0 |
| Modeling of basic digital hardware | 5.0 | 0.0 | 0.0 | 0 |
| Modeling of complex digital hardware | 10.0 | 0.0 | 0.0 | 0 |
| Verification approaches, testing of designs, verification tools, simulators | 3.0 | 0.0 | 0.0 | 0 |
| The verification plan, levels of verification and verification strategies | 2.0 | 0.0 | 0.0 | 0 |
| Architecting testbenches, stimulus and response, self-checking testbenches | 4.0 | 0.0 | 0.0 | 0 |
| PSL and assertion based verification | 4.0 | 0.0 | 0.0 | 0 |
| Total | 40 | 0 | 0 | 0 |
Grading Plan:
Letter Grade
Course Components:
Lecture
Grade Roster Component:
Lecture
Credit by Exam (EM):
No
Grades Breakdown:
| Aspect | Percent |
|---|---|
| Individual modeling projects | 30% |
| Verification projects - group assignment | 20% |
| Midterm Exam | 25% |
| Final Exam | 25% |
Representative Textbooks and Other Course Materials:
| Title | Author | Year |
|---|---|---|
| VHDL: Analysis and Modeling of Digital Systems | Zain Navabi |
ABET-CAC Criterion 3 Outcomes
(N/A)
ABET-ETAC Criterion 3 Outcomes
(N/A)
ABET-EAC Criterion 3 Outcomes
(N/A)
Embedded Literacies Info
(N/A)
Attachments
(N/A)
Additional Notes or Comments
(N/A)